Chip multiprocessors with multiple cache

This paper proposes a non inclusive cache implementation where any data item can be present only at one level in cache hierarchy. So, aggregate cache space available will be more and more data can be present on chip, hence reducing of chip communication. Advantage of implementing inclusion property is ease of maintaining coherence, since coherence has to be maintained only at the last level cache. This paper proposes a coherence protocol which is slight modification of existing protocols, to maintain coherence in non inclusive caches.

http://en.oboulo.com/non-inclusion-property-in-chip-multiprocessors-with-multi-level-cache-65044.html